Integrated circuits have become affordable and widely used because of at least two economies of scale in the semiconductor device manufacturing process. The first is the density at which electrical components can be fabricated into an integrated circuit. The second is the number of integrated circuits that may be fabricated at one time on a semiconductor wafer. Integrated circuits fabricated on a semiconductor wafer are then separated, by dicing, and packaged.
The typical packaging technique is to package one integrated circuit at a time using wires individually bonded to each conductive input and output pad of an integrated circuit. Since an integrated circuit may require a large number of bond wires, serial wire-bonding slows data propagation and is susceptible to high defect rates. A packaging technique that offers higher throughput and lower defect rates is wireless bonding.
Wireless bonding includes flip-chip and tape automated bonding (TAB). Flip-chip bonding involves depositing solder bumps onto the conductive pads of the integrated circuit, which are on the top of the integrated circuit die, flipping the die over, aligning the solder bumps to an interconnect layer (i.e., the wireless bonding media), and connecting the die to the interconnect layer by causing the solder bumps to flow. TAB, or TAB bonding, is accomplished by gang-bonding conductive fingers formed in tape to the conductive pads of an integrated circuit.
The prior art listed below describes the basic steps of a flip-chip technique as follows. Clean the bond pads. Activate the bond pads by immersing them in a Zinc (Zn) solution. Deposit a metal (e.g., Nickel (Ng)) onto the bond pads to a desired height. Deposit a compressible metal (e.g., Gold (Au)) that adheres well to solder. Deposit solder bumps onto the compressible metal.
A problem with the prior art methods is not so much in the materials that are used but how the materials are used. Present methods that use identical materials but in different ways exhibit widely low and inconsistent reliability.
Another problem that exists at the die level and not the wafer level is the ability to reliably form solder bumps on bond pads. A voltage difference exists between bond pads formed over different semiconductor materials (i.e., p-type and n-type). The materials under the bond pads act as minute batteries of different voltages. These voltage differences interfere with the plating of the bond pads. The present invention solves this problem in a manner the results in high and consistent reliability.
U.S. Pat. No. 6,028,011, entitled “METHOD OF FORMING ELECTRIC PAD OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SOLDER BUMP,” discloses a method of forming solder bumps on bond pads by carefully controlling the acidity, or pH, levels of solutions of metals used to form solder bumps. U.S. Pat. No. 6,028,011 does not disclose a method of solving the die-level problem described above, as does the present invention. U.S. Pat. No. 6,028,011 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,637,638, entitled “SYSTEM FOR FABRICATING SOLDER BUMPS ON SEMICONDUCTOR COMPONENTS,” discloses a method of using Palladium as a compressible metal that adheres well to solder. U.S. Pat. No. 6,637,638 does not disclose a method of solving the die-level problem described above, as does the present invention. U.S. Pat. No. 6,637,638 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,759,751, entitled “CONSTRUCTIONS COMPRISING SOLDER BUMPS,” discloses a method of using Palladium underneath the inexpensive metal (e.g., Ni) deposited to a desired height. U.S. Pat. No. 6,759,751 does not disclose a method of solving the die-level problem described above, as does the present invention. U.S. Pat. No. 6,637,638 is hereby incorporated by reference into the specification of the present invention.
A master thesis by Suwanna Jittinorasett, for the Virginia Polytechnic Institute and State University, entitled “UBM Formation on Single Die/Dice for Flip Chip Applications,” published on Aug. 25, 1999, describes a method of plating bond pads at the die level. However, the cleaning process described in the thesis would not result in high and consistent reliability, as would the method of the present invention.